The candidate will focus on developing Post-Silicon validation plan, debug tools, and infrastructure for Tesla’s custom SoCs and Platform designs for Autopilot and AI. As a Senior member in the Silicon Validation team, the candidate will interface with many different cross functional teams as well as external vendors/partners to create detailed bringup and validation test plans for the IPs within the SOC like CPU, GPU, NOC, Memory, ISP, Neural Net Accelerator etc., and apply the plan in emulation, post-silicon, and platform use cases. In addition, the candidate will be tuning the IP blocks inside the SoC for optimal power/functional performance, and troubleshoot complex hardware bugs and field returns. The candidate will regularly take part in hardware design and schematics review, firmware development, and building automated test infrastructures for running large volume of post silicon system level tests.

The ideal candidate will need to have a deep understanding of Silicon Architecture, especially around different blocks in SoC like compute blocks, caches, interconnects, clock, power, reset, interrupts, MMUs, different power management schemes, and interaction with board level components like DRAM, PCIe, Ethernet etc.